The development of monolithic microwave integrated circuits (MMIC's) has allowed superior performance at frequencies higher than non-integrated amplifiers of the past. Enhanced frequency response is provided in part by use of III-V semiconductor materials, and in part by the fact of integration on a single chip and the short very direct interconnections that allows. Integration, however, also presents some difficulties in that the opportunity to adjust discrete components to achieve a desired operating point is curtailed. As a result, it is sometimes difficult to accommodate for differences in operating characteristics caused by minor process variations which can occur over time from lot to lot.
One such problem can be illustrated with reference to FIG. 1 which shows a chip pattern for a typical prior art one-stage negative feedback amplifier and FIG. 2 which shows the circuit diagram for that amplifier. As shown in FIG. 1, an amplifier MESFET 11 is formed on a substrate 12 of semi-insulator material such as GaAs. It is seen that other elements of the amplifier are formed on the same substrate and metallized interconnections 20 are used to provide short and direct low inductance connections between such elements. External terminals 13a-17a are also provided for interconnecting the integrated circuit with the external world including inputs, outputs and bias power supplies. Metallic (e.g., gold) connecting wires 18 interconnect the external terminals 13a-17a with internal electrode pads 13b-17b and thus the integrated circuit elements.
As is well known in the art, the MESFET 11 includes source and drain regions interconnected by a channel. Formed on the source and drain regions are ohmic source S and drain D electrodes. A gate electrode G overlies the channel and as will be described below is formed in a gate recess.
In greater detail, the source S of the MESFET is grounded while the drain D is connected to the output terminal 17a and, via a diffusion resistor R.sub.L, to a drain bias voltage source V.sub.DD. The gate G has four connections: to ground via a diffusion resistor R.sub.B and a first capacitive element C.sub.l, to a gate bias voltage source V.sub.B via the same diffusion resistor R.sub.B, to an input terminal via a second capacitive element C.sub.2, and to the drain D via a feedback network comprising a resistor R and a third capacitive element C.sub.3.
A portion of the MESFET 11 is shown in cross section in FIG. 3a. It is seen that the substrate 12 includes a doped region 19 forming an active layer. Typically, the doped region 19 is formed by masking followed by ion implantation, usually with silicon ions implanted into the semi-insulative substrate. The doped region 19 typically extends to about 0.3 to 0.7 microns into the substrate and is formed to include a heavily doped source region 19a, a similarly heavily doped drain region 20a connected by a more lightly doped channel 22. Source S and drain D ohmic electrodes are formed on the respective source and drain regions. The partly completed device is then masked and etched to form a gate recess 21 crossing the channel 22 and located intermediate the source and drain. The recess forms a thinned cross sectional area of the channel which improves threshold voltage control while allowing the rest of the channel to remain thick to minimize parasitic resistance. Conventionally, the depth dr of the channel 21 is approximately 0.2 to 0.4 microns. Following etching, a Schottky metal gate G is formed in the recess 21 by conventional plating and liftoff techniques.
FIG. 3b is similar to FIG. 3a and serves to illustrate the problems which can arise from inadequate control of the etching process for forming the gate recess 21. As is appreciated, the wet etching process used to form the gate recess 21 is not always as controllable as desired. For example, the composition of the etching liquid may vary slightly from day to day, resulting in a differences in etching conditions from day to day. Similarly, the etching speed may vary due to slight temperature variations over time. Thus, the amount of etching (i.e., the depth dr of the gate recesses) may vary for devices produced on different wafers or lots. As shown in FIG. 3a, the dr.sub.1 of the recess is less than the value dr.sub.2 of the recess for the device of FIG. 3b. As a result, the cross sectional area of the channel under the gate G of FIG. 3a is greater than the cross sectional area of the same region for the device of FIG. 3b which results in undesirable differences in device characteristics from lot to lot.
As is known in the art, FET saturation current I.sub.DSS is dependent on (i.e., is proportional to) the cross sectional area of the channel 22 through which carriers (in this case electrons) flow from source to drain. When the depth dr of the recess 21 is large, the cross section of the channel 22 is small causing the device to saturate at a lower current level. Similarly, when the depth dr of the recess 22 is small, the cross sectional area of the channel 22 increases, increasing the saturation current level. The relationship between channel cross section (or recess depth) and saturation current I.sub.DSS for the devices of FIGS. 3a and 3b is shown in FIGS. 4a and 4b, respectively.
More particularly, FIGS. 4a and 4b show the DC characteristics for the FET's of FIGS. 3a and 3b, respectively, connected in the amplifier circuit of FIG. 2. The drain to source saturation current, that is, the maximum current through the device for a given drain bias V.sub.DD and load resistance R.sub.L with zero volts gate bias is seen to differ as a function of changes in the recess depth (or channel cross sectional area). When the recess depth is shallow as in FIG. 3a, creating a channel of large cross section, the saturation current I.sub.DSS1 is relatively higher than the saturation current I.sub.DSS2 for the device of FIG. 3b under the same operating conditions.
As a result, the quiescent operating points Q.sub.1, Q.sub.2 for a given gate bias (-V.sub.GG) are different and the amplifiers will perform in a different way for the same bias conditions. More particularly, as seen in FIG. 4a, the FIG. 3a amplifier will have a quiescent operating point Q.sub.1 of V.sub.Q1 at current I.sub.Q1 whereas the FIG. 3b amplifier will have a quiescent operating Q.sub.2 at a lower quiescent operating current I.sub.Q2 and a higher quiescent operating voltage V.sub.Q2 as illustrated in FIG. 4b. The undesirability of such variations in operating characteristics from lot to lot will be readily apparent.